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hv9123 general description the supertex hv9123 is a switch mode power supply (smps) controller subsystem that can start and run directly from almost any dc input, from a 12v battery to a rectifed and fltered 240vac line. it contains all the elements required to build a single-switch converter except for the switch, magnetic assembly, output rectifer(s) and flter(s). high-voltage, current-mode pwm controller + ? + ? + ? ref gen + ? + ? modulator comparator osc r s q current limit comparator comp osc in osc out fb vref bias vdd +vin pre-regulator/startup 8.6v 8.1v undervoltage comparator s r q v dd shutdown reset sense output error amplifier 4v to internal circuits 1.2v current sources to vdd 2v 5 (6) 6 (8) 4 (5) 12 (16) 13 (17) 1 (3) 7 (9) 16 (20) 11 (14) 15 (19) 8 (10) discharge -vin a unique input circuit allows the hv9123 to self-start directly from a high voltage input, and subsequently take the power to operate from one of the outputs of the converter it is controlling, allowing very effcient operation while maintaining input-to-output galvanic isolation limited in voltage only by the insulation system of the associated magnetic assembly. a 2% internal bandgap reference, internal operational amplifer, very high speed comparator, and output buffer allow production of rugged, high performance, high effciency power supplies of 50w or more, which can still be over 80% effcient at outputs of 1.0w or less. the wide dynamic range of the controller system allows designs with extremely wide line and load variations with much less diffculty and much higher effciency than usual. the exceptionally wide input voltage range also allows better usage of energy stored in input dropout capacitors than with other pwm ics. remote on/off controls allow either latching or nonlatching remote shutdown. during shutdown, the power required is under 6.0mw. for detailed circuit and application information, please refer to application notes an-h13, an-h21 to an-h24. functional block diagram note: pin numbers in parentheses are for plcc package. features ? 10 to 450v input voltage range ? <1.3ma supply current ? >1.0mhz clock ? >20:1 dynamic range @ 500khz ? 99% maximum duty cycle version ? low internal noise applications ? off-line high frequency power supplies ? universal input power supplies ? high density power supplies ? very high effciency power supplies ? extra wide load range power supplies supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
2 hv9123 absolute maximum ratings parameter value input voltage, v in 450v device supply voltage , v dd 15.5v logic input voltage -0.3v to v dd +0.3v linear input voltage -0.3v to v dd +0.3v preregulator input current, i in (continuous) 2.5ma operating junction temperature (t j ) 150 o c storage temperature -65 o c to +150 o c power dissipation: 16-lead soic 900mw 16-lead pdip 1000mw 20-lead plcc 1400mw stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin confgurations product marking 16-lead soic (ng) ordering information device package options 16-lead soic 9.90x3.90mm body 1.75mm height (max) 1.27mm pitch 16-lead pdip .790x.250in body .210in height (max) .100in pitch 20-lead plcc .353x.353in body .180in height (max) .050in pitch hv9123 HV9123NG-G hv9123p-g hv9123pj-g 1 16 1 16 4 20 1 2 16-lead pdip (p) 20-lead plcc (pj) 16-lead soic (ng) 16-lead pdip (p) 20-lead plcc (pj) y = last digit of year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking hv9123ng yww llllllll ccccccccc aaa y = last digit of year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv9123p llllllllll ccccccccccc aaa yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = ?green? packaging *may be part of top marking top marking bottom marking yyww aaa hv9123pj llllllllll ccccccccccc package may or may not include the following marks: si or package may or may not include the following marks: si or package may or may not include the following marks: si or supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
3 hv9123 electrical characteristics (unless otherwise specifed, v dd = 10v, +v in = 48v, discharge = -v in = 0v, r bias = 390k?, r osc = 330k?, t a = 25c.) sym parameter # min typ max units conditions reference v ref output voltage - 3.92 4.00 4.08 v r l = 10m? 3.84 4.00 4.16 r l = 10m?, t a = -55 to 125 o c z out output impedance # 15 30 45 k --- i short short circuit current - - 125 250 a v ref = -v in v ref change in v ref with temperature # - 0.25 - mv/c t a = -55 to 125c oscillator f max oscillator frequency - 1.0 3.0 - mhz r osc = 0 f osc initial accuracy 1 - 80 100 120 khz r osc = 330k - 160 200 240 r osc = 150k v osc voltage stability - - - 15 % 9.5v < v dd < 13.5v tc osc temperature coeffcient # - 170 - ppm/c t a = -55 to 125c pwm d max maximum duty cycle # 95 97 99 % --- d min deadtime # - 225 - ns --- minimum duty cycle - - - 0 % --- maximum pulse width before pulse drops out # - 80 125 ns --- current limit v lim maximum input signal - 1.0 1.2 1.4 v v fb = 0v t d delay to output # - 80 120 ns v sense = 1.5v, v comp 2.0v error amplifer v fb feedback voltage - 3.92 4.00 4.08 v v fb shorted to comp i in input bias current - - 25 500 na v fb = 4.0v v os input offset voltage - nulled during trim - --- a vol open loop voltage gain # 60 80 - db --- gb unity gain bandwidth # 1.0 1.3 - mhz --- z out out impedance # see fig. 1 --- i source output source current - -1.4 -2.0 - ma v fb = 3.4v i sink output sink current - 0.12 0.15 - ma v fb = 4.5v psrr power supply rejection # see fig. 2 db --- notes: # guaranteed by design. 1. stray capacitance on osc in pin must be 5pf. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
4 hv9123 electrical characteristics (cont.) (unless otherwise specifed, v dd = 10v, +v in = 48v, discharge = -v in = 0v, r bias = 390k?, r osc = 330k?, t a = 25c.) sym parameter # min typ max units conditions pre-regulator/startup +v in input voltage - 10 - 450 v i in < 10a; v cc > 9.4v +i in input leakage current - - - 10 a v dd > 9.4v v th v dd pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 v i prereg = 10a v lock undervoltage lockout - 7.0 8.1 8.9 v --- supply i dd supply current - - 0.75 1.3 ma c l < 75pf i q quiescent supply current - - 0.55 - ma shutdown = -v in i bias nominal bias current - - 20 - a --- v dd operating range - 9.0 - 13.5 v --- shutdown logic t sd shutdown delay # - 50 100 ns c l = 500pf, v sense = -v in t sw shutdown pulse width # 50 - - ns --- t rw reset pulse width # 50 - - ns --- t lw latching pulse width # 25 - - ns shutdown and reset low v il input low voltage - - - 2.0 v --- v ih input high voltage - 7.0 - - v --- i ih input current, input high voltage - - 1.0 5.0 a v in = v dd i il input current, input low voltage - - -25 -35 a v in = 0v output v oh output high voltage - v dd -0.25 - - v i out = 10ma - v dd -0.3 - - v i out = 10ma, t a = -55 to 125c v ol output low voltage - - - 0.2 v i out = -10ma - - - 0.3 v i out = -10ma, t a = -55 to 125c r out output resistance pull up - - 15 25 i out = 10ma pull down - - 8.0 20 pull up - - 20 30 i out = 10ma, t a = -55 to 125c pull down - - 10 30 t r rise time # - 30 75 ns c l = 500pf t f fall time # - 20 75 ns c l = 500pf note: # guaranteed by design. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
5 hv9123 test circuits detailed description preregulator the preregulator/startup circuit for the hv9123 consists of a high-voltage n-channel depletion-mode dmos transistor driven by an error amplifer to form a variable current path between the vin terminal and the vdd terminal. maximum current (about 20 ma) occurs when v dd = 0, with current re - ducing as v dd rises. this path shuts off altogether when v dd rises to somewhere between 7.8 and 9.4v, so that if v dd is held at 10 or 12v by an external source (generally the sup - ply the chip is controlling), no current other than leakage is drawn through the high voltage transistor. this minimizes dissipation. an external capacitor between vdd and vss is generally required to store energy used by the chip in the time be - tween shutoff of the high voltage path and the vdd supplys output rising enough to take over powering the chip. this capacitor should have a value of 100x or more the effective gate capacitance of the mosfet being driven, i.e., c storage 100 x (gate charge of fet at 10v) as well as very good high frequency characteristics. stacked polyester or ceramic caps work well. electrolytic capacitors are generally not suitable. a common resistor divider string is used to monitor v dd for both the undervoltage lockout cir - cuit and the shutoff circuit of the high voltage fet. setting the undervoltage sense point about 0.6v lower on the string than the fet shutoff point guarantees that the undervoltage lockout always releases before the fet shuts off. bias circuit an external bias resistor, connected between the bias pin and vss is required by the hv9123 to set currents in a se- ries of current mirrors used by the analog sections of the chip. nominal external bias current requirement is 15 to 20a, which can be set by a 390 to 510k? resistor if a 10v v dd is used, or a 510 to 680k? resistor if v dd will be 12v. a precision resistor is not required; 5% is fne. clock oscillator the clock oscillator of the hv9123 consists of a ring of cmos inverters, timing capacitors, and a capacitor dis- charge fet. a single external resistor between the osc in and osc out pins is required to set oscillator frequency (see graph). the discharge can either be connected to vss directly or connected to vss through a resistor used to set a dead time. one difference exists between the supertex hv9123 and competitive 9123s: the oscillator is shut off when a shutoff command is received. this saves about 150a of quiescent current, which aids in the construction of power supplies to meet ccitt specifcation i-430, and in other situations where an absolute minimum of quiescent power dissipation is required. reference the reference of the hv9123 consists of a stable bandgap reference followed by a buffer amplifer which scales the voltage up to approximately 4.0v. the scaling resistors of the reference buffer amplifer are trimmed during manufac - ture so that the output of the error amplifer, when connected in a gain of -1 confguration, is as close to 4.0v as possible. this nulls out any input offset of the error amplifer. as a con - sequence, even though the observed reference voltage of a specifc part may not be exactly 4.0v, the feedback voltage required for proper regulation will be. a 50k? resistor is placed internally between the output of the reference buffer amplifer and the circuitry it feeds (reference output pin and non-inverting input to the error + ? 60.4k 40.2k 1.0v swept 100hz - 2.2mhz tektronix p6021 (1 turn secondary) 0.1f +10v (v dd ) gnd (-v in ) (fb) error amp z out + ? reference v 2 10.0v 4.0v 100k1% 100k 1% psrr 0.1f 0.1v swept 10hz - 1.0mhz v 1 v 2 v 1 reference note: set feedback voltage so that v comp = v divide 1.0mv before connecting transformer. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
6 hv9123 amplifer). this allows overriding the internal reference with a low-impedance voltage source 6.0v. using an external reference reinstates the input offset voltage of the error am - plifer, and its effect of the exact value of feedback voltage required. in general, because the reference voltage of the supertex hv9123 is not noisy, as some previous examples have been, overriding the reference should seldom be nec - essary. because the reference of the hv9123 is a high impedance node, and usually there will be signifcant electrical noise near it, a bypass capacitor between the reference pin and vss is strongly recommended. the reference buffer ampli - fer is intentionally compensated to be stable with a capaci - tive load of 0.01 to 0.1f. error amplifer the error amplifer in the hv9123 is a true low-power dif - ferential input operational amplifer intended for around-the- amplifer compensation. it is of mixed cmos-bipolar con - struction: a pmos input stage is used so the common-mode range includes ground and the input impedance is very high. this is followed by bipolar gain stages which provide high gain without the electrical noise of all-mos amplifers. the amplifer is unity-gain stable. current sense comparators the hv9123 uses a true dual-comparator system with in - dependent comparators for modulation and current limiting. this allows the designer greater latitude in compensation design, as there are no clamps (except esd protection) on the compensation pin. like the error amplifer, the compara - tors are of low-noise bicmos construction. remote shutdown the shutdown and reset pins of the hv9123 can be used to perform either latching or non-latching shutdown of a converter as required. these pins have internal current source pull-ups so they can be driven from open-drain logic. when not used, they should be left open, or connected to vdd. output buffer the output buffer of the hv9123 is of standard cmos con - struction (p-channel pull-up, n-channel pull-down). thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external schottky diode clamping of the output is not required. shutdown reset output h h normal operation h h l normal operation, no change l h off, not latched l l off, latched l h l off, latched, no change truth table shutdown timing waveforms 50% t d 1.5v sense 0 t sd 50% 90% 90% vdd shutdown 0 t lw 50% 50% t sw 50% 50% t rw 50% t r 10ns t f 10ns t r , t f 10ns vdd shutdown 0 vdd reset 0 vdd output 0 vdd output 0 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
7 hv9123 typical performance curves psrr - error amplifier and reference 10 100 1k 10k 100k 1m output switching frequency vs. oscillator resistance 10k 100k 1m r osc () f out (hz) 80 70 60 50 40 20 10 0 -10 error amplifier open loop gain/phase r discharge vs. t off gain (db) phase ( o c) 180 120 60 0 -60 -120 -180 frequency (hz) 10 6 10 5 10 4 10 3 10 2 10 1.0 0.1 error amplifier output impedance (z 0 ) 0 -10 -20 -30 -40 -50 -60 -70 -80 1m 100k 10k bias resistance () 10 5 10 6 10 7 bias current (a) v dd = 10v psrr (db) frequency (hz) z 0 () r discharge () t off (nsec) r osc = 10k 100 1k 10k 100k 1m 10m frequency (hz) r osc = 1.0k r osc = 100k v dd = 10v 100 1k 10k 100k 1m 100 10 1.0 10 -1 10 10 1 10 2 10 3 10 4 10 5 10 6 10 4 10 3 10 2 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
8 hv9123 pin descriptions pin # description 1 nc 2 nc 3 +vin 4 nc 5 sense 6 output 7 nc 8 -vin 9 vdd 10 osc out pin # description 11 osc in 12 discharge 13 nc 14 vref 15 nc 16 shutdown 17 reset 18 comp 19 fb 20 bias pin # description 1 +vin - - - - 4 sense 5 output 6 -vin 7 vdd 8 osc out pin # description 9 osc in 10 discharge 11 vref 12 shutdown 13 reset 14 comp 15 fb 16 bias 16-lead soic (ng) 16-lead pdip (p) 20-lead plcc (pj) pin # description 1 +vin 2 nc 3 nc 4 sense 5 output 6 -vin 7 vdd 8 osc out pin # description 9 osc in 10 discharge 11 vref 12 shutdown 13 reset 14 comp 15 fb 16 bias supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
9 hv9123 16-lead soic (narrow body) package outline (ng) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 9.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ac, issue e, sept. 2005. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-16song, version g041309. d seating plane gauge plane l l1 l2 to p v iew side v iew vi ew a-a vi ew b vi ew b 1 e1 e a a2 a1 a a seating plane e b h h 16 1 note 1 note 1 (index area d/2 x e1/2) note: 1. this chamfer feature is optional. if it is not present, then a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator . supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
10 hv9123 16-lead pdip (.300in row spacing) package outline (p) .790x.250in body, .210in height (max), .100in pitch note 1 (index area) 16 1 d l a1 a a2 seating plane e e1 d1 d1 e a a side v iew to p v iew vi ew a - a ea eb b b1 v iew b vi ew b note: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. symbol a a1 a2 b b1 d d1 e e1 e ea eb l dimension (inches) min .130* .015 .115 .014 .045 .780 .005 .290 ? .240 .100 bsc .300 bsc .300* .115 nom - - .130 .018 .060 .790 - .310 .250 - .130 max .210 .035* .195 .023 ? .070 .810 ? .050* .325 .280 .430 .150 jedec registration ms-001, variation ab, issue d, june, 1993. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-16dipp, version b041009. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
11 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) hv9123 doc.# dsfp-hv9123 a040711 20-lead plcc package outline (pj) .353x.353in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .385 .350 .385 .350 .050 bsc .025 nom .172 .105 - - - .390 .353 .390 .353 .035 max .180 .120 .083 .021 .032 .395 .356 .395 .356 .045 jedec registration ms-018, variation aa, issue a, june, 1993. drawings not to scale. supertex doc. #: dspd-20plccpj, version c031111 .150 max .048/.042 x 45 o 1 . 075 max 3 8 13 18 d d1 e1 e t op vi ew v iew b a a2 a1 seating plane e note 1 (index area) .056/.042 x 45 o base plane .020 min b vi ew b b1 20 horizontal side v iew v ertical side vi ew note 2 .020max (3 places) r notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?201 1 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com

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